1. Field of the Invention
This invention relates to a sample-and-hold circuit used for an input portion of an analog-to-digital converter (hereinafter called as "A/D converter").
2. Description of Related Art
A sample-and-hold circuit is constituted of a transmission gate, or an analog switch, for converting a continuous analog signal to a discrete signal, and a holding capacitor for storing an output of the transmission gate between samples. Such a sample-and-hold circuit has been often used at an analog input portion of a successive approximation type A/D converter.
When the sample-and-hold circuit is constituted only of the transmission gate and the holding capacitor and when an analog driving source has a high output impedance, the CR time constant of the circuit becomes large, and therefore, a longer time is needed to charge or discharge the holding capacitor.
In order to charge and discharge the holding capacitor quickly, a sample-and-hold circuit including an operational amplifier has been proposed and come into wide use. The operational amplifier of the sample-and-hold circuit is connected between an input terminal of the sample-and-hold circuit and the transmission gate, and is built as a voltage follower by connecting its output to its inverting input terminal. Since the input impedance of the operational amplifier is very high, the holding capacitor can be charged and discharged quickly even if the analog driving source has a high output impedance, for instance such as of several deca-kilo ohm or above.
Such an operational amplifier is typically constituted of a plurality of MOS transistors, and a pair of the MOS transistors among them forms the differential amplifier by commonly connecting their sources to a constant current source in the operational amplifier. In order to operate the operational amplifier formed of the MOS transistors, the pair of the MOS transistors must be in an active mode. However, generally speaking, an MOS transistor does not amplify when the voltage difference between its gate and its source is less than its threshold voltage. For example, where the differential amplifier of an operational amplifier is formed of pMOS transistors, the source voltage of the pMOS transistor is no more than a power supply voltage V.sub.DD, for instance, 5 V. The threshold voltage Vth of the pMOS transistors is typically 1.5 V. Therefore, if an input voltage is in a range from 5 V (=V.sub.DD) to 3.5 V (=V.sub.DD - Vth), the differential amplifier of the operational amplifier is not activated. This limits the analog input voltage of the sample-and-hold circuit including the operational amplifier.